PATENT
A. Kranti, and N. Navlakha, “Multiple gate tunneling field effect transistor device for capacitorless dynamic memory,” India, 201621007078 (2016), pending.
PEER - REVIEWED JOURNALS
A. A. Bhatti, B. T. Archer, N. Navlakha, S. K. Banerjee and L. F. Register, "Semi-Classical Monte Carlo Study of the Impact of Tensile Strain on the Intrinsic Performance Limits of Monolayer MoS2 n-channel MOSFETs,” Journal of Applied Physics, 134, no. 20, 204302 (2023).
M. H. R Ansari, N. Navlakha, and N. El-Atab, "Engineered Vertically Stacked NSFET Charge Trapping Synapse for Neuromorphic Applications," ACS Applied Electronic Materials, Accepted (2023).
N. Navlakha, P. Jadaun, L. F. Register, and S. K. Banerjee, “Band Alignment in Black Phosphorus/Transition Metal Dichalcogenide Heterolayers: Impact of Charge Redistribution, Electric Field, Strain and Layer Engineering,” Journal of Electronic Materials, 52, 1474-1483 (2023).
A. A. Bhatti, N. Navlakha, D. M. Crum, S. K. Banerjee and L. F. Register, "Monte Carlo Study of Si, Ge, and In0.53Ga0.47As n-Channel FinFET Scaling: Channel Orientation, Quantum Confinement, Doping, and Contacts," IEEE Nanotechnology Magazine, 14, no. 6, 17-31 (2020).
M. H. R Ansari, N. Navlakha, J. Y. Lee, and, S. Cho, “Double-Gate Junctionless 1T DRAM with Physical Barriers for Retention Improvement” IEEE Transactions on Electron Devices, 67, no. 4, 1471-1479 (2020).
J.-T. Lin, W.-T. Sun, H.-H. Lin, Y. J. Chen, N. Navlakha, and A. Kranti, ”Raised Body Doping-Less 1T-DRAM with Source/Drain Schottky Contact,” IEEE Journal of Electron Devices Society, 7, 276-281 (2019).
M. H. R Ansari, N. Navlakha, J.-T. Lin, A Kranti, “Improving charge retention in capacitorless DRAM through material and device innovation,” Japanese Journal of Applied Physics 58 (SB), SBBB03 (2019).
M. H. R Ansari, N. Navlakha, J.-T. Lin, and A. Kranti, “1T-DRAM with Shell-Doped Architecture,” IEEE Transactions on Electron Devices, 66, no. 1, 428-435 (2018).
M. H. R Ansari, N. Navlakha, J.-T. Lin, and A. Kranti, “High Retention with n-Oxide-p Junctionless Architecture for 1T DRAM,” IEEE Transactions on Electron Devices, 65, no. 7, 2797 - 2803 (2018).
M. H. R. Ansari, N. Navlakha, J.-T. Lin, and A. Kranti, “Doping Dependent Assessment of Accumulation Mode and Junctionless FET for 1T DRAM,” IEEE Transactions on Electron Devices, 65, no. 3, 1205 - 1210 (2018).
N. Navlakha, and A. Kranti, “Overcoming the Drawback of Lower Sense Margin in Tunnel FET based Dynamic Memory along with Enhanced Charge Retention and Scalability,” Nanotechnology, 28, no. 44, article 445203 (2017).
N. Navlakha, and A. Kranti, “Insights into Operation of Planar Tri-gate Tunnel Field Effect Transistor for Dynamic Memory Application,” Journal of Applied Physics, 122, no. 4, article 044502 (2017).
N. Navlakha, J.-T. Lin, and A. Kranti, “Retention and Scalability Perspective of Sub 100 nm Double Gate Tunnel FET DRAM,” IEEE Transactions on Electron Devices, 64, no. 4, pp. 1561 - 1567 (2017).
N. Navlakha, J.-T. Lin, and A. Kranti, “Improved Retention Time in Twin Gate 1T DRAM with Tunneling Based Read Mechanism”, IEEE Electron Device Letters, 37, no. 9, 1127-1130 (2016).
N. Navlakha, J.-T. Lin, and A. Kranti, “Improving Retention Time in Tunnel Field Effect Transistor based Dynamic Memory by Back Gate Engineering”, Journal of Applied Physics, 119, no. 2, 214501 (2016).
CONFERENCES
N. Navlakha, and M. H. R Ansari, “Long-Term Potentiation and Depression with Vertically Stacked Nanosheet FET,” IEEE Latin American Electron Devices Conference, Accepted (2023).
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N. Navlakha, M. H. R Ansari, L. F. Register, and S. K. Banerjee “Comparative Study of Steep Switching Devices for 1T Dynamic Memory,” IEEE Latin American Electron Devices Conference, Poster, Accepted (2023).
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N. Navlakha, L. F. Register, and S. K. Banerjee, “Emerging 2D Materials for Tunneling Field Effect Transistors,” IEEE Latin American Electron Devices Conference, Poster, Virtual (2022).
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J. Randall, J. H.G. Owen, E. Fuchs, R. Santini, N. Navlakha, “Progress Toward 2D Nano Bipolar Junction Transistors,” International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, USA (2021).
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N. Navlakha, M. H. R Ansari, and A. Kranti, “TFET based 1T-DRAM: Physics, Significance and Trade-offs,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S, USA (2019).
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M. H. R Ansari, N. Navlakha, J.-T. Lin, and A. Kranti, “Architecture Evaluation for Standalone and Embedded 1T-DRAM,” IEEE Symposium on VLSI Technology, Systems and Application”, VLSI-TSA, Taiwan (2019).
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N. Navlakha, M. H. R Ansari, J.-T. Lin, and A. Kranti, “Performance Assessment of TFET Architectures as 1T-DRAM,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S, USA (2018).
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M. H. R Ansari, N. Navlakha, J.-T. Lin, and A. Kranti, “1T DRAM with Vertically Stacked n-Oxide-p Architecture,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, USA (2018).
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N. Navlakha, and A. Kranti, “Physical Insights on Junction Controllability for Improved Performance of Planar Trigate Tunnel FET as Capacitorless Dynamic Memory” IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, pp. 129-132, USA (2018).
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M. H. R Ansari, N. Navlakha, J.-T. Lin, and A. Kranti, “Influence of Material Parameters on the Performance of Accumulation Mode DRAM” International Conference on Solid State Devices and Materials, SSDM, Japan (2018).
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M. H. R. Ansari, N. Navlakha, J.-T. Lin, and A. Kranti, “Emerging FETs for Low Power and High Speed Embedded Dynamic Random Access Memory,” IEEE International Conference on VLSI Design, VLSID, India, pp. 422-427 (2018).
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N. Navlakha, J.-T. Lin, and A. Kranti, “Tunnel FET Capacitorless DRAM,” International Workshop on Physics of Semiconductor Devices, IWPSD, India (2017).
M. H. R. Ansari, N. Navlakha, J.-T. Lin, and A. Kranti, “Investigation of Junctionless Transistor based DRAM,” International Workshop on Physics of Semiconductor Devices, IWPSD, India (2017).
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N. Navlakha, and A. Kranti, “Performance Assessment of Tunnel Field Effect Transistors based Capacitorless Dynamic Memory,” abstracts of International Symposium on Integrated Functionalities, ISIF, India (2017).
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M. H. R. Ansari, N. Navlakha, J.-T. Lin, A. Kranti, “Junctionless Capacitorless Dynamic Random Access Memory,” abstracts of International Symposium on Integrated Functionalities, ISIF, India (2017).
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N. Navlakha, J.-T. Lin, and A. Kranti, “Design Optimization of Tunnel FET for Dynamic Memory Applications,” IEEE Electron Devices and Solid-State Circuits, EDTM, Taiwan (2017).
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N. Navlakha, J.-T. Lin, and A. Kranti, “Twin gate Tunnel FET based capacitorless dynamic memory”, IEEE International Symposium on VLSI Technology, Systems and Application, VLSI-TSA, Taiwan (2017).
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N. Navlakha, J.-T. Lin, and A. Kranti, “Optimization of Back Gate Workfunction, Alignment and Bias for Charge Retention in TFET based DRAM,” IEEE International Conference on Emerging Electronics, India, ICEE, India (2016).
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N. Navlakha, J.-T. Lin, and A. Kranti, “Enhanced Retention Characteristics in Double Gate Tunnel FET based DRAM,” International Conference on Solid State Devices and Materials, SSDM, Japan (2016).
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N. Navlakha, and A. Kranti, “Impact of Back Gate Workfunction on Performance of TFET based DRAM,” International Workshop on Physics of Semiconductor Devices, IWPSD, India (2015).
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N. Navlakha, L. Garg, D. Boolchandani, and V. Sahula, “Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals,” International Symposium on VLSI Design and Test, VDAT, Communications in Computer and Information Science (CCIS, volume 382), Springer, India (2013).
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