Computational Design of Emerging Materials and Devices
My research focuses on novel devices and materials - device physics, simulation & modeling. I have worked on 2D materials, advanced transistors as FinFETs, Tunnel FET, Junctionless transistors, and have explored other FETs as Z2FET, IMOS, FED, TCCT, and memory design of Capacitorless DRAM and SRAM architecture. I am interested in innovating device designs and material systems for NEXT-GEN computing with improved performance, focusing on energy-efficient electronics.
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Overview of my research work
Need for New devices, Materials & Design
The future of computing is driven by data-intensive applications that include Artificial Intelligence (AI), Internet of Things (IoT), and networking. Every minute, a tremendous amount of data is produced., all generated data need to be stored, copied, and retrieved. These require systems with low power, increased storage density, faster architecture, and energy efficiency and so, we need new devices, materials, and designs, which is the focus of my work.
Data generated every minute
2D MATERIALS & HETEROSTRUCTURE
Mentors: Prof. Sanjay K. Banerjee and Prof. Leonard F. Register , UT Austin
Study electronic properties using Density Functional Theory (DFT), identifying material systems for low power transistors such as Tunnel FET. In-depth understanding of band tunability through strain, material and layer engineering, environment of surrounding materials, and external field. Such tunability offers flexible application to electron-hole bilayer-TFETs, reconfigurable FETs, electro-optical modulators, rectifier diodes, contacts, photo conductors and light emitting devices.
TUNNEL FET as CAPACITORLESS DRAM
Advisor: Dr. Abhinav Kranti, IIT Indore
Proposed innovative device designs, physical insights, and a systematic analysis for improved performance, reducing trade -offs of TFET based DRAMs. The work demonstrates device perspective, where various metrics of dynamic memory are regulated by device architecture (misaligned, twin, and planar tri-gate TFET), geometry (gate lengths, film thickness), parameters (oxide thickness, gate workfunctions), biases and temperature.
Misaglined DG TFET, proposed for 1T-DRAM
Collaboration Projects
Charge Trapping Synaptic Device for Neuromorphic Applications
Investigation of charge trapping memory for synaptic transistor that can mimic the learning behaviors of human brain. Design device for energy-efficient artificial synapse and understand the underlying device physics to improve synapse features for image recognition/detection.
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Semi-classical Monte Carlo Modeling of FinFETs
Understand and model the essential underlying physics of nanoelectronics device which involves Monte Carlo (MC) simulations, Boltzmann transport equation (BTE)-based drift-diffusion-energy balance simulations. Assessed the impact of n-channel scaling towards the end of CMOS roadmap for Si, Ge, InGaAs FinFETs, with results showing Ge being the future at lower gate lengths.
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Architecture Evaluation of Junctionless Transistors for 1T-DRAM
Assessment of junctionless transistors for embedded and stand-alone capacitorless DRAM. The advanced designs used conduction and storage regions separated by physical barriers to attain scalable - low power 1T DRAM. The work highlights device physics and progress in the architecture of these devices to operate efficieny as DRAM.
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Process Simulation of Bipolar Junction Transistor
Performed process simulation of implant and diffusion processes to understand impact of dopant distribution on 2D bipolar junction transistors. The work highlights early progress to devlop a delta doped pn juction for bipolar transistor for insights into the fabrication process of to realize a novel 2D-3D-2D NPN transistor.